1. Field of the Invention
The present invention relates to a process of manufacturing a Bi-CMOS type semiconductor integrated circuit in which a bipolar transistor and a CMOS transistor are formed on the same semiconductor substrate.
2. Prior Art
Conventionally, in a Bi-CMOS type integrated circuit, bipolar devices and CMOS devices have been formed on the same chip so that the driving capability of the CMOS devices are enhanced by the bipolar devices in order to obtain high responsive CMOS. Accordingly, although the Bi-CMOS type integrated circuits have exhibited both bipolar and CMOS characteristics, they have been able to exhibit excellent functions such as high speed operation, high density, high resistant-voltage, high driving capability, low power consumption and the like.
The high speed bipolar integrated circuit has a thick oxide film which is formed by a deep selective oxidation process (which will be denoted hereinbelow as "LOCOS-1"), corresponding to the thickness of epitaxial growth, in order to obtain an isolation.
FIGS. 1(a) to 1(c) show the process steps of the above-mentioned LOCOS-1.
As shown in FIG. 1(a), after an N.sup.+ buried diffusion layer 2 being formed on a P type Si substrate, an N type epitaxial layer 3, a thin oxide film 4 and an Si.sub.3 N.sub.4 film 5 are formed thereover successively in that order.
Then, as shown in FIG. 1(b), the Si.sub.3 N.sub.4 film 5 and the thin oxide film 4 are selectively removed by a well-known photoetching technic, and thereafter, using the Si.sub.3 N.sub.4 film 5 as a mask, the epitaxial layer 3 is etched down to a thickness which is about one-half of the original thickness thereof.
Next, as shown in FIG. 1(c), a heavy doped layer 6 preventing a channel is formed on the part of the epitaxial layer 3 which has been etched, by implanting B.sup.+ ions into that part.
Then, using the Si.sub.3 N.sub.4 film 5 as a mask, a selective oxidation process is carried out to form an isolation oxide film 7 which reaches the N.sup.+ buried diffusion layer 2, as shown in FIG. 1(c). Thereafter, the Si.sub.3 N.sub.4 film 5 and a thin oxide film 4 are removed so as to complete the isolation.
As mentioned above, in a high speed bipolar device, a thick oxide film should be formed for isolation after silicon is etched, in order to reduce the isolation capacity and substrate capacity so as to obtain a high speed performance and in order to completely isolate devices from each other.
Meanwhile, in a CMOS device, the thickness of an oxide film for isolation has not to be as thick as that of the bipolar device since the device operation is controlled by a surface channel, and accordingly, a selective oxidation process in which etching of silicon is not required (which will be denoted hereinbelow as "LOCOS-2") is used. The process steps of this LOCOS-2 will be simply explained with reference to FIGS. 2(a) to 2(b).
As shown in FIG. 2, a thin oxide film 12 and a Si.sub.3 N.sub.4 film 13 are at first laminated and selectively formed on a P type Si substrate 11.
Then, using this Si.sub.3 N.sub.4 film 13 as a mask, a selective oxidation process is carried out to form an isolation oxide film 14 as shown in FIG. 2(b) so as to complete the isolation.
Thus, in the CMOS device, the isolation can be attained by the isolation oxide film which is thinner than that of the bipolar device, and accordingly, the step of etching silicon is unnecessary.
As mentioned above, although both LOCOS-1 and LOCOS-2 are not different from each other in view of the use of a thick oxide film for isolation, which is formed by selective oxidation and which will be hereinbelow denoted as "field oxide film", the former is distinguished from the latter because etching of an epitaxial layer is necessary in order to prevent formation of a large surface step due to cubic expansion caused by a thick oxide film formed by selective oxidation. These field oxide films are used in the subsequent steps of self-aligningly forming several diffusion layers such as a base, an emitter, a source, a drain and the like, and contacts, that is, they are very effective since the process steps can be simplified and the area of the devices can be reduced. In the case of the bipolar, the thickness of the oxide film is in the range of 1 to 2 .mu.m, and in the case of the CMOS, it is in a range of 0.5 to 1 .mu.m.
With a conventional high speed Bi-CMOS, the isolation by the LOCOS-2 which is mainly taken into consideration for the function of the CMOS has been used in general since it has simple isolation steps.
However, with such a high Bi-CMOS, a part of the characteristic of a high-speed bipolar has been sacrificed if the LOCOS-2 is used for the isolation. In particular, there has been raised such a problem that the substrate capacity and an isolation capacity are increased.
Meanwhile, if the LOCOS-1 isolation process is applied for a Bi-CMOS structure, the so-called bird's beak 7a as shown in FIG. 1(c) becomes large, which is caused by a lateral growth of an oxide film when the isolation oxide film 7 is formed. That is, there has been raised the defect of incurring an increase in the area of isolation. This causes a fatal disadvantage such that the packing density for the CMOS section is lowered, and further, conventional CMOS design rules which are designed with the LOCOS-2 cannot be used directly although the characteristic of the bipolar device can be ensured. In the Bi-CMOS technology, the design rules which are compatible with those of the CMOS is in general strongly required in order to effectively use abundant CMOS circuit libraries. As a result, the above-mentioned LOCOS-2 has been mainly used for isolation.
Further, although it may be considered easily that the process of the LOCOS-1 and the process of the LOCOS-2 are merely used successively, not only the processes become long and complicated, that is, particularly in the case of self-aligningly producing a high-speed bipolar by selectively oxidizing polysilicon, the selective oxidation should be repeated three times, but also the number of heat treatments are increased so that the control of the diffusion layer is difficult. Accordingly, it has been not useful.
As mentioned above, even though either processes is used for the Bi-CMOS, there has been raised problems such that the packing density for a CMOS transistor is lowered, and conventional CMOS design rules cannot be used. Further the process becomes lengthy thus, accordingly, is not useful, and such processes are technically unsatisfactory.